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Responsibilities

  • Perform verification planning
  • Testbench development using UVM methodologies
  • Implement functional verification of mixed-signal ASICs
  • Failure analysis and resolution, coverage analysis and population
  • Digital/mixed-signal modeling
  • Develop directed/constrained-random test generation, gate-level simulations
  • Develop analog mixed-mode simulations (AMS)
  • Perform hardware/software co-verification
  • Regression debug support and other flow/infrastructure development

Required Skills and Qualifications

  • MS or PhD in Electrical Engineering or Computer Engineering and design or verification experience preferably in mixed signal products
  • Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, Vera)

Preferred Skills and Qualifications

  • Able to work closely with digital/analog designers, applications engineers, firmware developers, and manufacturing test to support pre-silicon verification
  • Knowledge of signal processing and System Verilog Assertions
  • Ability to build, evaluate, debug, and improve verification processes
  • Ability to mentor junior engineers in verification methodology