Submit your resume

"*" indicates required fields

Max. file size: 2 MB.
Drop files, or upload here

Description

Data movement bottlenecks have informed poor design decisions in nascent computer architectures for AI. We use silicon photonics to break through the existing data-movement bottlenecks, and we’re re-architecting the entire AI hardware stack to take advantage of the 1000x increases in bandwidth and performance. We are creating a single training solution that will outperform the world’s largest AI supercomputers. Backed by Bill Gates, Luke Nosek, Ali Partovi, Dara Khosrowshahi, and other reputable Silicon Valley investors.

About the job

We are looking for an experienced Physical Design Manager to join our fast paced engineering organization working on cutting-edge technologies in the AI HW acceleration space. In this position you will lead the implementation of complex SoCs by building and managing a team of high-performing engineers and driving innovation at advanced process nodes. You will work closely with architecture and design teams to ensure high-quality results.

What you will be doing:

  • Responsible for hiring, mentoring, and managing a team of engineers to deliver physical designs for complex AI products
  • Define and develop methodology using best-in-class tools and techniques for physical implementation and verification
  • Collaborate with teams across the organization to ensure high quality product deliverables
  • Develop and track schedules while setting team priorities
  • Interface with foundry partners, tool vendors, and design service providers as required
  • Own responsibility for streaming final designs to foundry partners

Requirements

  • 15+ years of industry experience
  • 5+ years of direct management experience with a proven track record of building high-performance teams
  • Hands-on experience with industry standard P&R tools and methodologies through the entire implementation process (synthesis, floorplanning, CTS, P&R, timing closure, power analysis, EMIR analysis, DRC, LVS, etc)
  • Experience with deep sub-micron design challenges and solutions
  • Successful tape out of 1M+ gate devices
  • Excellent communication, leadership, and time management skills