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The Engineer is responsible for I/O library development, which encompasses the design, simulation, characterization and validation of I/O pad libraries. Also responsible for the definition of the ESD methodology and to specify the chip and IP level ESD requirements. Design ESD protection devices and circuits to meet design requirements. Develop test structures to characterize Si for ESD/LUP properties. Drive the development of design rules based on Si characterization data. Interface with foundry on ESD library and ESD/LUP rule development activities. Engineer needs to have a holistic view of ESD/EOS protection for mixed signal CMOS circuits and the ability to pull pieces together to insure no gaps or blind spots in strategy.

Duties include:

  • Design, simulate, and optimize I/O circuits and ESD structures
  • Characterization and modeling of I/O libraries to support mixed signal design flow
  • Release and maintain I/O libraries and models
  • Must understand ESD and latch-up requirements
  • Drive ESD sign off methodology for chip & block level projects
  • Technical lead capable of pulling together engineer’s, new & existing methodologies to tie ESD-Latchup-IO methodologies together & get buy in from BU’s

Job Requirements

  • Holistic view of ESD/EOS protection for mixed signal CMOS circuits
  • Strong fundamentals in ESD circuit design, layout and testing
  • Relevant experience in IO design including CMOS circuit design, ESD and latch-up requirements, physical verification, and characterization
  • Chip level ESD signoff experience
  • Must understand layout and be able to guide layout engineers
  • Proficiency with Cadence schematic capture, layout, and simulation tools
  • Ability to work independently and lead or be part of a technical team
  • Effective oral and written communication a must
  • Experience in IBIS model generation is a plus