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Education
- Bachelor’s degree in Electrical Engineering (or similar). Master’s or PhD degree preferred.
Experience
- Extensive prior experience of digital and analog mixed-signal verification (minimum 10 years).
- Practical experience of chip top-level integration and verification, with prior experience of SystemVerilog and python preferable.
- Prior experience of driving the top-level verification plan and developing the verification process and methodology.
- Proven track record and hands-on experience enabling chip design blocks in mass production, i.e. multiple tape-outs.
- Extensive prior experience of, ideally large, CMOS image sensor chips (preferably minimum 10 years).
- Using already-established expertise, provide design verification leadership, technical mentorship and guidance to team members.
- Prior experience in ion-sensitive field-effect transistor (ISFET) sensor technology is a plus.
Knowledge, Skills, Abilities
- Excellent communication skills (verbal, written, presentation) – be a proactive and humble listener, able to receive, process, and act upon feedback from team members.
- Create and verify VerilogA and Verilog models.
- Run analog simulations and extracted simulations
- Create and run digital test cases.
- Expert/proficient with industry-standard Cadence analog design and verification tools.