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As a PDK Engineer, you will assist in the design of high-performance mixed-signal ASICs by developing & integrating technology files, models & decks (DRC, LVS, and PEX) in support of our PDKs. Collaborate closely with design teams, foundries, and our silicon technology team to develop and verify PDKs. You will apply expertise to EDA methodology including development, qualification, automation, and support as well as evaluation & development of new tools & flows.

Responsibilities

  • Work closely with design & layout teams to support tape out of IC designs
  • Install, customize and test foundry PDKs
  • Develop and qualify physical verification decks
  • Customize and test our analog/mixed-signal environment
  • Support parasitic extraction
  • Support IC tapeout methodology

Required Skills and Qualifications

  • BS in Electrical or Computer Engineering and 5+ years of proven experience in related CAD field or MS in Electrical Engineering
  • A good understanding of front to back analog/mixed signal design methodology
  • Experience with PDK installation, customization and QA
  • Experience with PDK development and validation
  • Ability to effectively support layout & design teams
  • Able to demonstrate programming knowledge in Perl, SKILL, Tcl, Python and/or shell scripting
  • A hardworking individual who possesses strong organizational & interpersonal skills, and demonstrates versatility in handling a wide range of CAD methodology issues
  • Expertise in one or more of the following areas: Developing Cadence dfII technology files, netlisting, simulation & Pcells OR Development of physical verification decks in Calibre OR Parasitic extraction and simulation (XRC, QRC or Star-RC)

Preferred Skills and Qualifications

  • MS Electrical Engineering or Computer Engineering and 5+ years of relevant experience
  • Experience working with revision control systems. Perforce is a plus
  • Familiarity with Calibre PERC and/or Insight
  • Familiarity with EM/EMIR methodology