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As a principal digital design engineer, you will be responsible for the design of the company’s machine learning processor. You will actively participate in IP architecture, performance/area/power optimization, and development. You will also participate in SOC architecture, design and verification as well as hardware/firmware/software co-design.

Responsibilities:

  • Architecture of the company’s IP blocks including aggressive optimization for performance, power, and area
  • Implementation of company IP RTL logic in Verilog
  • Contribution to verification of the company’s IP and SOC logic
  • Performance and power verification and validation of the company’s IP and SOC

Qualifications:

  • Versatility, independent thinking, and general ability to get things done!
  • 15+ years of experience working on high performance IP and ASIC designs
  • Bachelor/Masters/PhD in Electrical/Computer Engineering/Engineering Science
  • Expert knowledge of Hardware Description Languages (Verilog/VHDL)
  • Comfortable with C++
  • Deep and broad understanding of processor/computer architecture
  • Knowledge and understanding of the full ASIC design flow
  • Experience with any of high frequency logic design, scalar and vector processor architecture, GPU architecture and programming models, digital signal processing hardware, SoC architecture, memory sub system architecture, real time hardware/firmware systems or deep learning is very beneficial