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As a senior design verification engineer, you will be responsible for the verification of the company’s machine learning processor, at both unit, multi-unit, and SoC level. You will actively participate in definition of verification strategy, planning, and implementation of every aspect of verification, including a large component of performance validation.

An excellent candidate is versatile, independent, and have a general ability to get things done! Creative thinkers who look for new and better ways to verify designs, while being extremely comfortable with tried and true ways, will excel in this role.

Qualifications:

  • Bachelor/Masters in Electrical or Computer Engineering
  • Excellent programming skills in C++ and other languages
  • Expert knowledge of Verilog and SystemVerilog Experience in UVM, constrained random verification, coverage implementation and closure
  • Experience in performance verification
  • Deep interest in computer architecture, under-the-hood details of machine learning frameworks, GPU programming and methods for efficient parallelization of deep learning execution is very beneficial