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You will design embedded processor sub-systems, interface busses, memory and controller interfaces and other embedded processor digital IP for sub-45nm mixed-signal CMOS Audio SoCs in a full custom ASIC design flow. You will contribute directly, or coordinate with other team members on, the specification, modeling, design, test, physical design, and validation of custom CMOS Audio SoCs. This includes ensuring your digital design IP meets specification, interfacing with the other digital subsystems, optimizing for area and current consumption, and communicating with the firmware and other teams supporting silicon development. You will validate the custom digital IP and contribute to system-level testing and silicon evaluation.
This position requires an individual skilled in making good circuit implementation decisions which lead to high performance, bug free silicon. Our business relies on the ingenuity and inventiveness of our design group to solve our customers’ problems. The ideal candidate will be comfortable working at the RTL/HW level as well as optimizing C/Assembly firmware code.
You will interface with other engineering teams within the business unit including your AI/DSP, digital, analog and firmware design counterparts for Audio SoCs. Our engineering teams work together to deliver high-quality execution and first-silicon success.
- Develop complex Audio SoC/chip Architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.
- Evaluate processor IP for architecture and PPA requirements
- Target processor evaluations into FPGAs for application validation
- Support CPU/MCU PPA optimization for audio and AI applications
- Support pre-silicon verification of digital sub-systems
- Work with PD team to ensure proper synthesis, PnR, STA and ATPG of digital sub-systems
- Work with Applications, DV and FW teams to ensure debug and tools support for code development
- BSEE or BSCE + 5 years experience or Master’s + 3 years or PhD
- 3-5 years of professional experience in CPU and/or MCU digital design engineering
- In-depth knowledge of Verilog RTL language
- Fundamental understanding of processor architecture and organization
- Experience designing and verifying complex state-machines
- Experience with design/waveform browsing for both RTL verification and GLS
- Full understanding of the digital design flow from architecture, RTL design, verification, and synthesis
- Experience with revision control/configuration management systems
- Organized and detailed with strong communication skills
- Possess outstanding analytical and problem-solving skills
- Results-oriented, self-driven and thrives in a dynamic environment
- Experience integrating ARM, RISC-V, or other commercially available processor cores
- Experience with DMA engines, Arbiters, APB/AHB/AXI or other AMBA/NoC bus interfaces
- Experience trading off system design between digital, analog and firmware
- Strong lab and silicon validation skills
- Basic understanding of CMOS transistors
- Experience with scripting and automation
- Knowledge of Python, Perl and Tcl is ideal