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This confidential company is strategically bringing on a hands-on technical DV leader. In this role, the verification expert will be collaborating cross-functionally with a talented team of design engineers in developing cutting-edge integrated circuits (ICs). This individual will have first-hand involvement in diversification as the organization ventures into new markets, next-generation products, and applications.

Technical Responsibilities

Verification Planning and Strategy

  • Develop verification plans and strategies based on design specifications and requirements to ensure thorough testing and validation of semiconductor designs
  • Define verification methodologies, test benches, and test cases to effectively verify and validate digital designs, including RTL (Register Transfer Level) designs

Testbench Development and Simulation

  • Join a development team that architects and designs advanced verification methodology and SV-UVM testbenches
  • Create internal testbench framework to support all project testbenches

Debugging and Documentation

  • Analyze verification results and debug issues to identify root causes and implement effective solutions, working closely with design and verification teams.
  • Document verification processes, methodologies, and results, and provide regular updates and reports to project stakeholders.


  • Master’s degree or Ph.D. in Electrical Engineering
  • 7-10+ years of relevant industry experience
  • Leadership experience is a bonus, but not required
  • Proficiency in verification languages and methodologies, such as SystemVerilog, UVM
  • Professional expertise related to semiconductor design principles, digital logic, and ASIC/FPGA design flows